A broadband receiver protection limiter for FET based integrated circuits

Radar and radio receivers must be capable of surviving high power incident signals without incurring damage to power sensitive components while allowing the receiver to function under normal operating conditions. In this investigation a FET based two stage limiter with a threshold detector was designed and manufactured on a 0.5 um pHEMT GaAs process. The electrical requirements over a 4 GHz to 11 GHz frequency range, include +40 dBm pulse operation with less than +24 dBm, output power leakage. The circuit measures less than 0.8 dB insertion loss and noise figure. The design has the capability of operating as a limiter during the insertion loss state and as a high isolation switch when the DC power is removed. The unpowered state provides over 20 dB of isolation between the input and output. An active detector sense circuit is utilized to set the output leakage to less than 24 dBm. The sense circuit operates at less than 5 milliwatts of DC power.