A behavioral model for a wideband RF analog-to-digital converter

We describe a behavioral model of an interleaving RF-to-digital ADC. The ADC has an input bandwidth of over 3 GHz, and is a 16-bit interleaved digitizer. The model includes both analog and digital parts, describing the analog nonlinearity and frequency response, and digital impairments such as jitter, thermal noise, and interleaving errors. The model is implemented in a commercial simulator. The model is built from simulated data to enable the design of RF system architecture prior to the availability of first silicon.