DocumentCode :
3704258
Title :
Parallel Pipeline on Heterogeneous Multi-processing Architectures
Author :
Andrés Rodríguez;Angeles Navarro;Rafael Asenjo;Antonio Vilches;Francisco Corbera;María Garzarán
Author_Institution :
Andalucia Tech, Univ. de Malaga, Malaga, Spain
Volume :
3
fYear :
2015
Firstpage :
166
Lastpage :
171
Abstract :
We address the problem of providing support for executing single streaming applications implemented as a pipeline of stages that run on heterogeneous chips comprised of several cores and one on-chip GPU. In this paper, we present an API that allows the user to specify the type of parallelism exploited by each pipeline stage running on the CPU multicore, the mapping of the pipeline stages to the devices (GPU or CPU), and the number of active threads. Using as case of study a real streaming application, we evaluate how these parameters affect the performance and energy efficiency of a heterogeneous on-chip processor (Exynos 5 Octa) that has three different computational cores: a GPU, an A15 quad-core and an A7 quad-core. We also explore some memory optimizations and find that while their performance impact depends on the granularity type, they usually reduce energy consumption.
Keywords :
"Pipelines","Graphics processing units","Multicore processing","System-on-chip","Instruction sets","Parallel processing"
Publisher :
ieee
Conference_Titel :
Trustcom/BigDataSE/ISPA, 2015 IEEE
Type :
conf
DOI :
10.1109/Trustcom.2015.627
Filename :
7345643
Link To Document :
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