Integrated FFT accelerator and inline bin-rejection for automotive FMCW radar signal processing

This paper presents a comparative study of two setups of FMCW radar signal processing for automotive applications. In one setup, the signal processing is done on a traditional DSP architecture. In a new proposed setup, the FFT engine/accelerator is integrated. In addition to that, a unit for performing inline rejection of FFT bins is inserted into the processing datapath. It is shown that the proposed architecture can reduce the number of clock cycles required to perform the FMCW signal processing and it can also reduce the radar memory usage compared to the implementation on a DSP architecture.