Modeling of DG-Tunnel FET for low power VLSI circuit design

This paper presents the analytical potential modeling of Double Gate (DG) Tunnel Field Effect Transistor (TFET) at 50 nm channel length. In this model approach the channel potential is sum of a long channel potential and a short channel perturbation along with the whole structure rather than just the Si/SiO2 interface or the channel centre. For the validation of our analytical modeling approach we compared our result with reported data which verify our proposed design.