Title :
Test scenario selection for concurrency testing from UML models
Author :
Mahesh Shirole;Rajeev Kumar
Author_Institution :
Computer Engineering and Information Technology Dept., Veermata Jijabai Technological Institute, Matunga, Mumbai 400 019, India
Abstract :
Parallel systems have potentially exponential number of execution interleaving sequences. Each execution interleaving sequence can be used as a test scenario to evaluate the correctness of the system. Both the exponential interleaving space and non-deterministic execution make testing concurrent systems a challenging task. Concurrency errors are classified as synchronization, data-race, data inconsistency, starvation, and deadlock. A good test suite must have test scenarios that uncover above all classes of errors. Selecting test scenarios to uncover above errors needs a systematic analysis of test scenarios to classify them into one of concurrency behaviors. In this paper, we propose an approach to analyze test scenarios from UML models using a state-based classifier. First, we present an extension to UML models to represent data access-tags, which help generating data-access traces. Then, we generate test scenarios from extended UML models using existing test scenario generation techniques. After that, we analyze test scenarios using enhanced state machine diagram (ESMD) classifier for concurrency behaviors, like sequentilization, synchronization, blocking, and non-blocking scenarios. Experimental results show ESMD classifier classifies test scenario accurately thereby helping to design test suite for concurrency testing. Selected test scenarios achieve better concurrency behavior coverage and avoid false test scenarios.
Keywords :
"Unified modeling language","Concurrent computing","Message systems","Testing","Synchronization","Software","Java"
Conference_Titel :
Contemporary Computing (IC3), 2015 Eighth International Conference on
Print_ISBN :
978-1-4673-7947-2
DOI :
10.1109/IC3.2015.7346739