Voltage and time margin analysis for wireline links in high dimensional design spaces

Evaluating the time and voltage margin (vtMargin) of a wireline link across all possible corner cases is deemed unfeasible using time-domain methods. Statistical methods provide estimates at a fraction of time, at the potential cost of accuracy and neglecting the nonlinear behaviors of various link elements. We present a methodology to calculate the vtMargin of memory and serial links in a time-efficient manner while considering nonlinear behaviors of active blocks. Using a small initial dataset, regression analysis is performed to find multi-variable multi-order equations, which are then exhaustively evaluated across all possible combinations of corner cases to find a more comprehensive histogram representing the margin spread in the link.