• DocumentCode
    3705480
  • Title

    Challenges of high-speed channel design on GPU accelerated system

  • Author

    Chun-Lin Liao;Terence Rodrigues;Bhyrav Mutnury

  • Author_Institution
    Dell Enterprise Server Group, Taipei, Taiwan, R.O.C.
  • fYear
    2015
  • Firstpage
    221
  • Lastpage
    224
  • Abstract
    High speed servers continue to deploy graphics processing units (GPUs) in them for large volume data computation. Robustness of signal integrity on the high-speed channel is an important factor in these high performance computing (HPC) system designs. In this paper, the simulation and validation / debugging procedure of a 1U / 2 socket rack server that can support up to 4 GPU units was used as exampled to investigate the challenges on such high-speed channel design.
  • Keywords
    "Graphics processing units","Topology","Stripline","Servers","Impedance","Microstrip","Silicon"
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging and Systems (EPEPS), 2015 IEEE 24th
  • Print_ISBN
    978-1-5090-0038-8
  • Type

    conf

  • DOI
    10.1109/EPEPS.2015.7347166
  • Filename
    7347166
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3705480