Dynamic current reduction of CMOS digital circuits through design and process optimization

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.