Energy-efficient Level Shifter topology

Level Shifters (LS) are essential components of integrated circuits with multiple power supply. They work as voltage scaling interfaces between different power domains. In this paper, we present an energy-efficient level shifter with low area topology. It requires only one power rail and can operate nearby the threshold voltage. We validated the proposed topology with simulations on an IBM 130nm CMOS technology. We compared our topology with traditional LS, like the Differential Cascode Voltage Switch (DCVS) or the Puri´s topology. The proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri´s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. In addition, our level shifter was the only one capable to work at 35% of the nominal supply.