An efficient hardware architecture for interpolation filter of HEVC decoder

In most video coding standard, motion compensation MC is applied to remove temporal redundancy and reduce the size of bit stream significantly. In the decoder, the reconstructed MV (Motion Vector) is generated from the prediction error and neighboring information. However, due to the finite sampling the motion of blocks does not match exactly in the integer positions of samples grid. The High efficiency video coding standard HEVC introduced 7 taps filter and 8 taps filter for the interpolation of ¼ and ½ luminance sub positions respectively which can give a better precision in the inter prediction process. Furthermore, the profiling of the HM reference software proves that the interpolation filter consume more than 50% of the complexity of Motion Compensation block in the HEVC decoder with random access configuration. Therefore, a new flexible hardware architecture for half and quarter fractional pixels used in the interpolation filter is proposed in this paper. This architecture can process the whole fractional positions of 4×4 PU (prediction unit) in only 30 clock cycles and support a maximal throughput of QFHD@30fps at 185 MHZ. The implementation is performed with the technology TSMC 0.18 um.