Design of electrodes and circuits for cell trapping on CMOS

We discuss design issues related to realization of a CMOS Lab-on-Chip (LoC) platform for sorting of cells and microorganisms. The proposed platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform electrical field. DEP depends on the permittivity of the cells, its size and shape and also the permittivity of the medium. This paper discusses the important issues of electrode design using the built-in metal layers of the CMOS process for the most effective trap for single or group of cells. Given the need to perform the operation in real-time, in-situ impedance monitoring of the trapping function is also suggested. We present simulation results for three electrode designs, and CMOS implementation for one, namely the three-dimensional (3D) octapole electrode geometry. It also presents an analog front end for impedance monitoring of biological targets as they are repositioned on electrodes due to DEP in real-time. Experimental results with yeast cells validate the design.