Si based tunnel FETs : Status and perspectives

Tunnel field effect transistors (TFET) are regarded as the best concept for ultra low power devices. The physical limit of MOSFETs, namely the minimum slope of 60 mV/dec (@ 300K), is lifted for TFETs. It is expected that TFET circuits will outperform subthreshold electronics at voltages around 0.2 V. However, the fabrication of well performing n- and p-type TFETs is still a great challenge. The occurrence of trap assisted tunneling (TAT) appears as one of the major obstacles to achieve steep slopes. Numerous TEFT designs, exploiting point and line tunneling, as well as various materials are presently under investigation. In this presentation, the major focus will be on strained silicon n- and p-type nanowire (NW) TFETs and first complementary inverters. In addition, an outlook of novel designs and materials, such GeSn, will be given.