Towards three-dimensional integration of two-dimensional active logic circuits using low temperature multilayer stacking of GFETs

In this paper, 3D integration using multiple stacking of 2D active device layers is proposed as a new path of future 3D integration technology that can reduce the active power consumption by more than 50%. Two layers of Graphene FETs on PET substrates were successfully stacked using low temperature processes (<;150 C) and the influences of the stacking process on the electrical characteristics of lower level graphene devices were analyzed. While this is the first attempt to fabricate double stacked 2D device layers transferrable to other device substrate, no critical degradation to the devices has been observed.