Electrical characterisation of horizontal and vertical gate-all-around Si/SiGe nanowires field effect transistors

This paper report the technological routes used to build horizontal and vertical gate all-around (GAA) Field-Effect Transistors (FETs) using both Si and SiGe NanoWires (NWs). Horizontal Si and SiGe nanowires FETs are characterized in back gate configuration. Vertical devices using Si nanowires (NWs) show good characteristics with an I_ON/I_OFF ratio close to 10⁶ and sub-threshold slope around 145 mV/decade. Finally, vertical SiGe devices also obtained with the same technological process present an I_ON/I_OFF ratio from 10³ to 10⁴ but also poor dynamics which can be explained by the high interface traps density.