DocumentCode :
3706345
Title :
A novel approach to generate self-aligned Ge/SiO2/SiGe gate-stacking structures in a single fabrication step
Author :
Wei-Ting Lai;Kuo-Ching Yang;Ting-Chia Hsu;Po-Hsiang Liao;Thomas George;Pei-Wen Li
Author_Institution :
National Central University, ChungLi, Taiwan, 320, Republic of China
fYear :
2014
fDate :
6/1/2014 12:00:00 AM
Firstpage :
1
Lastpage :
2
Abstract :
We demonstrated a novel, self-aligned gate-stack heterostructure of Ge-quantum dot (QD)/SiO2/SiGe-shell on Si with superior interfacial properties in a single step of selective oxidation of a SiGe pillar over a Si3N4 buffer layer on Si substrate. Ge metal-oxide-semiconductor (MOS) capacitors exhibit a quite low interface trap density on the order of 1011 cm-2eV-1, and Ge n-MOSFETs show good turn on and off features with a subthreshld slope of 175 mV/dec and Ion/Ioff > 106.
Keywords :
"Silicon","Logic gates","Silicon germanium","Substrates","MOSFET","Capacitance-voltage characteristics","Fabrication"
Publisher :
ieee
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2014 IEEE
Print_ISBN :
978-1-4799-5676-0
Type :
conf
DOI :
10.1109/SNW.2014.7348582
Filename :
7348582
Link To Document :
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