Analysis of delay time in subthreshold CMOS circuits operating at ultra-low supply voltage

The speed of subthreshold CMOS circuits is analyzed by circuit simulation. In particular, the dependences on drain-induced barrier lowering (DIBL) and load capacitance are evaluated and compared with CMOS circuits operating at normal supply voltage (V_dd). It is found that the speed of subthreshold circuits is much more degraded by DIBL than that of normal circuits because the peak transient drain current is more lowered by DIBL. On the other hand, it is also found that the effect of DIBL does not depend on load capacitance.