Title :
Minimum operation voltage of 6T-SRAM cell composed of 90Å bulk-FinFET considering oxide trap, high temperature, and variability
Author :
Youngsoo Seo;Duckseoung Kang;Sungwon Yoo;Dogyun Son;Hyungcheol Shin
Author_Institution :
Inter-university Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Gwanak-ro, Gwanak-gu, Seoul 151-742, Republic of Korea
fDate :
6/1/2014 12:00:00 AM
Abstract :
Mixed mode TCAD simulation using hydrodynamic transport model was performed for SRAM cell composed of 90Å silicon Bulk-FinFET. In case of worst-case trapping combination in SRAM and at high temperature (375K), read static noise margin (RSNM) is reduced by 16.1% compared to the case with empty trap and at 300K. In addition, regarding statistical variability including work function variation (WFV), random dopant fluctuation (RDF), and line-edge roughness (LER), minimum operation voltage of SRAM is about 0.36 V when minimum RSNM is 20 mV.
Keywords :
"Resource description framework","Electron traps","SRAM cells","FinFETs","Logic gates"
Conference_Titel :
Silicon Nanoelectronics Workshop (SNW), 2014 IEEE
Print_ISBN :
978-1-4799-5676-0
DOI :
10.1109/SNW.2014.7348601
