Simulation of grain-boundary traps effect for 3D vertical gate NAND flash memory cell : From structure geometry to trap description

3D NAND Flash is the most promising memory architecture which can increase capacity continuously without aggressive scaling-down. The performance variability of the memory cell induced by the grain boundaries (GBs) of the poly-Si channel is a major concern. In this work, a full 3D simulation is performed to study the threshold voltage variability. The impact of the 3D structure geometry on the variation induced by the GB traps is discussed. In addition, a discrete-trap approach is also proposed to reflect the true behavior of the GB traps. A smaller variation in the discrete-trap approach is observed due to the local trap effect.