Title :
M7: Oracle´s Next-Generation Sparc Processor
Author :
Aingaran, Kathirgamar ; Jairath, Sumti ; Konstadinidis, Georgios ; Leung, Serena ; Loewenstein, Paul ; McAllister, Curtis ; Phillips, Stephen ; Radovic, Zoran ; Sivaramakrishnan, Ram ; Smentek, David ; Wicki, Thomas
Abstract :
The Oracle Sparc M7 processor more than triples the throughput of the Sparc M6 processor, while increasing per-thread performance, power efficiency, and I/O bandwidth. M7 contains 32 8-thread, dual-issue, out-of-order Sparc cores. To minimize L3 cache hit latency, M7 features a partitioned L3 cache, with a novel on-chip network for communication between the cache partitions, coherence control, and memory. Memory bandwidth is more than 3 times that of the Oracle Sparc M6 processor. On-chip accelerators providing query filtering and decompression can provide another order of magnitude performance increase for these tasks. M7 keeps power consumption at a minimum through multiple power-saving techniques. M7 scales to 32-processor shared memory multiprocessing systems (SMPs). Coherent shared memory is also supported between SMPs in a cluster. Such a cluster is robust against both communication and SMP failure. Application data integrity guards against pointer-related software vulnerabilities without slowing the processor. Fine-grained memory migration supports concurrent garbage collection.
Keywords :
cache storage; I/O bandwidth; L3 cache hit latency; Oracle Sparc M6 processor; Oracle Sparc M7 processor; Oracle next generation Sparc processor; SMP failure; application data integrity; cache partitions; coherence control; coherent shared memory; concurrent garbage collection; fine-grained memory migration; memory bandwidth; on-chip accelerators; on-chip network; per-thread performance; pointer-related software vulnerabilities; power efficiency; query filtering; shared memory multiprocessing systems; Computer architecture; Memory management; Microprocessors; Multicore processing; Parallel architectures; Program processors; System-on-chip; memory hierarchy; microarchitecture implementation considerations; multicore/single-chip multiprocessors; on-chip interconnection networks; parallel architectures; processor architectures; support for reliability; support for security;
Journal_Title :
Micro, IEEE