Design of high gain amplifier using on-chip transformer by neutralization

A high frequency and high gain amplifier using standard 65 nm TSMC technology is presented in this paper. A gain of the proposed amplifier was boosted by inserting on-chip transformer which inverts amplifier´s output phase to neutralize gain limiting parasitic capacitors. To control stability issue of the transformer induced positive feedback amplifier under the environments of process variations, variable neutralizer capacitors with variable capacitor value by body node biasing are suggested. The theory, simulation and measurement are shown in this paper. An implementation prototype is evaluated using on-wafer proving. The amplifier showed peak gain of 30 dB and noise figure of 4.6 dB under 8.9 mW power consumption with 1V power supply condition. The measured IIP3 was -26 dBm.