Scaling impact on design performance metric of sub-micron CMOS devices incorporated with halo

Leakages and short channel effects (SCE) impose challenges in the designing of CMOS devices as the device feature size enters the nanoscale regime. Advanced process design of CMOS devices are crucial in countering the limitations impose by SCE. This paper investigates the advantages of implementing the halo process into the design of the submicron-CMOS devices. Critical device performance merits and CV characterizations were explored as the device is scaled. Although the use of halo degraded slightly the performance for typically long channel transistor, the merging of halo implants at short transistor shows improvement with high stability of threshold voltage and low off-current. The Drain-induced barrier lowering (DIBL) specifically for the 45nm pMOS and nMOS alone had reduced to 25% and 41% respectively. With careful optimal choice for heavy doped halo of and reverse body biasing, it simultaneously relieved total leakage current by adjusting the threshold voltage.