DocumentCode :
3710842
Title :
3D integration by wafer-level aligned wafer bonding
Author :
V. Dragoi;J. Burggraf;F. Kurz;B. Rebhan
Author_Institution :
EV Group, DI E. Thallner 1, 4782-St. Florian/Inn, Austria
fYear :
2015
Firstpage :
185
Lastpage :
188
Abstract :
Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.
Keywords :
"Wafer bonding","Bonding","Plasma temperature","Metals","Silicon","Substrates","Surface treatment"
Publisher :
ieee
Conference_Titel :
Semiconductor Conference (CAS), 2015 International
ISSN :
1545-827X
Print_ISBN :
978-1-4799-8862-4
Type :
conf
DOI :
10.1109/SMICND.2015.7355203
Filename :
7355203
Link To Document :
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