A genetic algorithm based approach to pipelined memory-aware scheduling on an MPSoC

Although multicore designs seem to be a viable replacement of single core designs, the new architecture comes with its share of problems. A main problem is that we do not have the necessary software tools and techniques to utilize the power of multiple processors. This added a burden on the shoulders of software and tool developers to devise techniques to harvest the powerful architecture. One very needed technique is effectively scheduling tasks on the system processing cores while managing the memory budget. The end goal is increased parallelism for better performance. In this paper, we present a genetic algorithm based approach to pipelined scheduling on a multi-processor system-on-a-chip as an integrated step with memory partitioning. Results on real life benchmarks showed the effectiveness of our techniques.