• DocumentCode
    3712355
  • Title

    Dynamic core scaling: Trading off performance and energy beyond DVFS

  • Author

    Wei Zhang;Hang Zhang;John Lach

  • Author_Institution
    ECE Department, University of Virginia, Charlottesville, VA, USA 22904
  • fYear
    2015
  • Firstpage
    319
  • Lastpage
    326
  • Abstract
    Dynamic voltage and frequency scaling (DVFS) is commonly employed on modern superscalar processors to reduce energy when peak performance is not needed or allowed. As technology scales, the effectiveness of DVFS is limited by the shrinking viable supply voltage range. This work proposes dynamic core scaling (DCS) to extend performance-energy tradeoff capabilities in superscalar processors. DCS ensures that programs run at a given percentage of their maximum speed and, at the same time, minimizes energy consumption by dynamically adjusting the active superscalar datapath resources. Evaluations using an 8-way superscalar processor implemented on 45nm circuit infrastructure show that DCS is more effective in performance-energy tradeoffs than DVFS at the high performance end. When used together with DVFS, DCS saves an additional 20% of a full-size core´s energy on average. At the minimum operating voltage, DVFS stops reducing energy, while DCS is still able to achieve an average of 46% further energy reduction.
  • Keywords
    "Program processors","Calibration","Energy consumption","Pipelines","Registers","Monitoring","Voltage control"
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2015 33rd IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/ICCD.2015.7357120
  • Filename
    7357120