A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits

Since asynchronous circuits consume power only when activities actually happen, the conventional serial communication scheme where the embedded clock is always transmitted and the clock and data recovery (CDR) circuit is continuously working is very wasteful for connecting asynchronous circuit cores. This paper proposes a new serial communication scheme for asynchronous circuits where the power consumption of the line drivers in the transmitter and the deserializer in the receiver are reduced to almost 0 for the period when no data is transmitted. The proposed scheme is based on a new encoding mechanism where four voltage levels are used in order to embed a clock signal explicitly and a new sampler that extracts the clock and data without using PLL/DLL based circuits. This paper shows overall ideas of the proposed scheme and some initial HSPICE simulation results using 28nm and 130nm device technologies.