Hardware implementation of low-overhead data aided timing and Carrier Frequency Offset correction for OFDM signals

In this paper a trained timing synchronization method using a matched filter and Carrier Frequency Offset synchronization method based on a modified correlation scheme is implemented in hardware for Orthogonal Frequency Division Multiplexing. MATLAB System Generator is used to target a Virtex-6 FPGA on the ML605 Xilinx evaluation board, with an optimized number of board resources utilized. A complex pseudo-noise sequence is used as a preamble for timing. The employed training sequence for frequency synchronization consists of only one pilot symbol, distinguishing this system from most approaches which rely upon multiple pilot symbols. By reducing the number of symbols required for the training period, it is possible to increase throughput. In addition, to ensure that the system has flexibility and is not protocol specific, the system allows for a variable number of FFT sizes and pilot symbol design parameters to be used. Performance of the system is shown to improve over an Additive White Gaussian Noise channel by implementing the design in comparison to not compensating for the distortion.