Design and validation of a mixed-signal correlator using a multiple-input floating gate transistor

The design and validation of an architecture of a CMOS mixed-signal correlator in VLSI technology based on the Multiple-Input Floating Gate MOS Transistor is introduced. The key element of this architecture is a single transistor with 513 inputs. The system includes one pair of configurable shift registers, a comparator stage with hysteresis and an output stage. The correlator is designed for processing sequences of 256 bits and is validated for a technology process of 0.35μm. The novel proposed architecture is described here and its operation is validated using simulation tools. We discuss ways to resolve the problems of simulation generated by the use of the 513-input floating gate device. The architecture is proposed to operate at low voltage.