Prototyping system for USB3.0 link layer using synthesizable assertions and partial reconfiguration

There are several researches, which identify the following two problems as main bottlenecks of post-silicon validation: bug detection/localization and coverage calculation. Although FPGA prototyping is considered as pre-silicon verification the coverage calculation and bug localization are as much challenging as for post-silicon phase. This article presents a novel approach to solve the above mentioned issues by embedding synthesizable assertions into prototype. The experiment has been performed on USB3.0 link layer prototype. During the experiment all injected errors have been successfully detected and functional coverage has been calculated. The main drawback of the proposed approach is unacceptable resource utilization which, was solved by adding reconfigurable regions into FPGA. Synthesis results are presented for group of assertions intended to test entry/exit functionality of low power mode which show that the FPGA resource overhead is less than two percent of super speed USB link prototype. This approach gives us ability to implement USB design and all assertions for single test in one FPGA with acceptable timing results and minor area overhead.