FPGA implementation of Hilbert transformer based on lattice wave digital filters

The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an effective way of implementing the lattice wave digital structure of the Hilbert transformer with canonic signed digit code (CSDC) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow ripple carry adders. This increases the speed of overall filter structure compared to the conventional way of implementing the filter with CSDC coefficients. The proposed Hilbert transformer is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.