Propagation delay and its robustness study of inverter topologies

This paper analyzes the delay and delay variability by realizing the inverter circuit in different logic families. Speed plays a major role in today´s VLSI circuits and even a fraction of delay affects the circuits by a large factor. Variability, just like other factors such as delay, area and power has emerged to be a key factor in designing circuits. CMOS families comprises of both single-ended and differential type logic circuits. The outputs of the inverters are investigated at 32-nm technology node in HSPICE model. The logic family with least variability and delay are reported to aid the designer in selecting the best logic family as per the requirement.