CMOS phase frequency detector and charge pump for multi-standard frequency synthesizer

An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. The mechanisms for widening the phase error detection range and eliminating the dead zone are applied in the proposed PFD. To maintain a fast locked performance and a stable loop bandwidth for multi-standard frequency synthesizer applications, a programmable structure and sub-circuits are developed. Implemented by 0.18μm CMOS process, the PFD has correct logic function, whereas the charge pump is stable in the output range of 0.4V~1.4V with a current mismatch less than 1.5%, and the power consumption is 2.3mW under a 1.8V supply.