A study on system-level ESD stress simulation using circuit simulator

In this paper, we proposed and examined the simulation method for system-level ESD using ESD source model, transmission line model, and ESD protection circuit model on the existent circuit simulator. We also evaluated the simulation method by comparison of the simulated and measured results using test PCB and ESD-gun. In this experiment, we targeted the voltage waveforms at input signal pin of the D-F/F IC on the test PCB when the ESD stress is injected to the signal line on the PCB. From experimental results, it is found that the proposed simulation method can simulate system-level ESD stress if the characteristics of the ESD protection circuit can measure.