Low-dropout regulator design using reverse nested miller compensation

A multi-stage low-dropout (LDO) linear regulator with reverse nested miller compensation is presented. The multi-stage structure can derive the high dc voltage gain to insure the load/line regulation. The error amplifier adopts cascading technique using reverse nested miller compensation with current buffer for the low supply voltage stable frequency response. The proposed LDO was implemented by UMC 0.11μm CMOS process. The designed LDO linear regulator works under the input voltage of 1.5V-3.3V and provides up to 60mA load current for an output voltage of 1.23V. The experimental results revealed that the LDO provides a full load transient response of less than 30μs setting time and less than 18mV Overshoots and undershoots. Moreover, the dropout voltage is 18mV at 60mA loading, and quiescent current is 50μA when output current is 60mA.