• DocumentCode
    3717066
  • Title

    FNOCEE: A framework for NoC evaluation by FPGA-based emulation

  • Author

    Daniel Pfefferkorn;Achim Schmider;Guillermo Pay?-Vay?;Martin Neuenhahn;Holger Blume

  • Author_Institution
    Institute of Microelectronic Systems, Leibniz Universit?t Hannover, Appelstr. 4, 30167, Germany
  • fYear
    2015
  • fDate
    7/1/2015 12:00:00 AM
  • Firstpage
    86
  • Lastpage
    95
  • Abstract
    This paper introduces FNOCEE, a framework for the evaluation of NoC-based many-cores systems by FPGA-based emulation. It uses a task graph-oriented approach to model applications, while a hardware-accelerated genetic algorithm is employed to find close-to-optimal solutions to the task mapping problem. The proposed genetic algorithm is analyzed in detail, e.g., in terms of mutation rate and number of elite individuals. In order to illustrate the framework´s capabilities, several case studies have been performed, wherein scalability of relevant parallel applications is investigated with regard to the number and type of available processing cores and the generated traffic load as a result of inter-task communication.
  • Keywords
    "Computer architecture","Genomics","Bioinformatics","Genetic algorithms","Computational modeling","Emulation","Topology"
  • Publisher
    ieee
  • Conference_Titel
    Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on
  • Type

    conf

  • DOI
    10.1109/SAMOS.2015.7363663
  • Filename
    7363663