A CMOS High Resolution Multi-Edge Delay Generator

This paper describes a new architecture of a high-resolution multi-edge delay generator for on-chip testing applications, which enables a timing generation with a sub-gate delay resolution to be fully implemented in any purely digital CMOS process. The proposed delay generator utilizes multi edge-triggered oscillators to achieve a high resolution based on the Vernier technique with low power, a smaller footprint and without requiring a high speed clock reference compared to the conventional delay generators. In addition, the maximum measured delay range of the proposed design can be improved without degrading the achievabl5ve resolution. Simulation results based on 0.09 μm CMOS technology shows an achievable delay resolution of 14.6 ps with a reference input frequency at 500 MHz.