• DocumentCode
    3717710
  • Title

    Stability and performance of classical digital phase-locked loop in discrete-time settings

  • Author

    Nur Syazreen Ahmad;Widad Ismail

  • Author_Institution
    Sch. of Electr. &
  • fYear
    2015
  • Firstpage
    1445
  • Lastpage
    1450
  • Abstract
    Many classical phase-locked loops (PLLs) are treated as linear continuous-time systems in the locked condition. While this is useful for sinusoidal input and output signals, the PLLs are more accurately modeled in the z-domain particularly when (i) digital phase detector is used; and (ii) the inputs and outputs are in digital form such as those mostly used in data communications. This paper presents a stability and performance analysis of classical digital phase-locked loops (CDPLLs) in discrete-time domain which is based on the induced ℓ2 norm objective. The result is formulated in the form of a linear matrix inequality (LMI) search which is computationally tractable. A simple application to a CDPLL consisting of a Butterworth filter is presented to illustrate the effectiveness of the result compared to the existing one.
  • Keywords
    "Approximation methods","Voltage-controlled oscillators"
  • Publisher
    ieee
  • Conference_Titel
    Control, Automation and Systems (ICCAS), 2015 15th International Conference on
  • ISSN
    2093-7121
  • Type

    conf

  • DOI
    10.1109/ICCAS.2015.7364580
  • Filename
    7364580