DocumentCode
3718187
Title
160 GHz parametric passive frequency doubler in CMOS 180nm technology
Author
Beng-Meng Chen; Zuo-Min Tsai
Author_Institution
Department of Electrical Engineering, and Avanced Institute of Manufacturing with High-tech Innovations, National Chung Cheng University, Chiayi, Taiwan
fYear
2015
Firstpage
1
Lastpage
2
Abstract
A parametric CMOS passive frequency doubler is reported in this paper. The circuit is implemented in 180 nm CMOS but oses a conservative 0.5um gate length and produces an output between 150GHz and 162 GHz with a minimum measured conversion loss of 19.15 dB . The maximum output power is -26.9 dBm by -4.25dBm input power. The proposed design series a transmission line at the transistor source and series a 500 Ohms resistance at the transistor body in order to improve the performance.
Keywords
"CMOS integrated circuits","CMOS technology","Schottky diodes","Varactors","Harmonic analysis","Silicon germanium","BiCMOS integrated circuits"
Publisher
ieee
Conference_Titel
Electromagnetics: Applications and Student Innovation Competition (iWEM), 2015 International Workshop on
Type
conf
DOI
10.1109/iWEM.2015.7365065
Filename
7365065
Link To Document