Reliability behaviors of an exposed die FCCSP on a substrate with ultra-low CTE laminate material

Flip chip package has been reported to be an ideal package solution of high bandwidth devices because of a lower power loss and a short transmission route of signal. However, some failure modes such as solder joint crack, delamination of substrate or low-k delamination within IC were often found after reliability verification. One of the key factors of failure is attributed to the mismatch of CTE values between Si chip (4 ppm) and substrate (tens ppm), and ultra-low CTE laminate materials are really needed to improve the reliability to automotive-level. In this study, a 1/2/1 substrate with a dimension of 12 mm × 12 mm × 0.22 mm was made by laminating low-CTE or low-Young´s modulus prepreg on a 100 μm thick core. FCCSPs with four types of core and PP-like build-up material were assembled and tested to understand the effect of selected material properties on the reliability response. The simulation results revealed that the effects of selected material properties such as low CTE and low Young´s modulus on the warpage behavior were not apparent. Also, the warpage of the tested FCCSPs might not be the dominated factor to affect the reliability performance. Simulate induced stress/strain during reliability test would be the major factor to decide the reliability performance of solder joints. The FCCSP having the highest maximum strain within the solder joints would fail after thermal cycling test. Low CTE material could reduce simulate maximum strain within the solder joints. In addition, the effect of low CTE seemed to be more prominent than that of low Young´s modulus on simulate maximum strain value. By numerical analysis and reliability test, beneficial effect of prepreg with low-CTE and low Young´s modulus on the reliability response had been confirmed.