Partial TMR in FPGAs Using Approximate Logic Circuits

TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable, with a low granularity, and can provide an optimal balance between reliability and overheads. The proposed approach has been validated using fault injection.