Physical Design Methodologies for Soft Error Mitigation Using Redundancy

This paper demonstrates methodologies for designing soft-error hardened logic on commercial foundry processes. Physical design flows employ standard CAD tools to provide spatial separation that alleviates risk of multiple node charge collection upsets. To demonstrate and compare the proposed techniques, an advanced encryption standard (AES) encryption engine is implemented with the proposed methodologies. The methodologies incur an area overhead of 3.4× for a self-correcting, transient immune TMR design and 1.6× for a design using TMR flip-flops with non-redundant logic providing only single-event upset mitigation, over a non-redundant design. Power dissipation increases to 4.82× and 2.4×, respectively.