DocumentCode :
3719458
Title :
Leakage current minimisation and power reduction techniques using sub-threshold design
Author :
Hippolyte Djonon Tsague;Bhekisipho Twala
Author_Institution :
Council for Scientific and Industrial Research (CSIR), Modelling and Digital Science (MDS), Pretoria, South Africa
fYear :
2015
Firstpage :
146
Lastpage :
150
Abstract :
Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and radio frequency identification bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to recharge the batteries while at the same time dramatically decreasing the device leakage currents. The use of sub-threshold techniques can be a powerful way to create circuits that consume dramatically less energy than those built using standard design practices. In this research, a SOI device was built to compare their electrical characteristics using Silvaco software. The comparisons were focused on three main electrical characteristics that are threshold voltage, sub-threshold voltage and leakage current. It was found that SOI devices are ideal candidates for low power operation.
Keywords :
"Transistors","Logic gates","Threshold voltage","CMOS integrated circuits","Leakage currents","Electric potential","Integrated circuit modeling"
Publisher :
ieee
Conference_Titel :
Information Society (i-Society), 2015 International Conference on
Type :
conf
DOI :
10.1109/i-Society.2015.7366877
Filename :
7366877
Link To Document :
بازگشت