Fast and accurate power estimation for application-specific instruction set processors using FPGA emulation

This paper presents an FPGA accelerated power estimation methodology for a Cadence Tensilica Xtensa LX5 ASIP. Based on hybrid functional level (FLPA) and instruction level power analysis (ILPA), the model can be mapped onto an FPGA together with the functional emulation. This enables fast and accurate estimation of application-specific power consumption and energy per task at early design stages which is crucial for power-aware design of instruction set extensions. The approach allows both hardware and software designers to optimize their implementations for power efficiency. The methodology for the ASIP and considerations for FPGA implementation are described and validated against GTL power simulation on different benchmarks. Results yield a %MAE of less than 7.0% and NRMSE of less than 6.9%. Finally, instruction set extensions for traffic sign detection are evaluated on real-world image sizes. It is shown that performance is improved by 11.2x while still reducing required energy by 10.5x.