Session 4: Signal processing on reconfigurable architectures

The aim of this session is to present recent advances in signal processing implemented on field programmable reconfigurable arrays (FPGA) and coarse grained reconfigurable arrays (CGRA). In the first paper a hardware architecture of the Soft-output CANcellation (SCAN) algorithm used to decode polar codes is presented. This codes achieve the capacity of various communication channels for infinite code-lengths. The proposed design allows to obtain higher data rate than other solutions, as well as less decoding iterations. In the second paper a real-time FPGA module for automatic audio indexing is presented. It is based on the Mel-Frequency Cepstral Coefficients (MFCC) features. The Xilinx System Generator tool was used for implementation. Experiments proved that the system is able to provide an 80% classification accuracy for 4 music genres. In the last paper an IEEE-802.11a/g orthogonal frequency-division multiplexing receiver block for wireless communication systems is presented. It was implemented on CGRA processor/coprocessor model and synthesized for an FPGA device. The authors report speed-ups from x2.8 to x9.3 over RISC processors solutions.