DocumentCode
3719804
Title
Image tiling for embedded applications with non-linear constraints
Author
Vitor Schwambach;S?bastien Cleyet-Merle;Alain Issard;St?phane Mancini
Author_Institution
Univ. Grenoble Alpes, TIMA, F-38031 Grenoble, France, CNRS, TIMA, F-38031 Grenoble, France
fYear
2015
Firstpage
1
Lastpage
8
Abstract
Tiling is a key aspect of the design of embedded image processing applications, due to local memory constraints. To maximize system performance, the designer must select a suitable tile size that balances data transfers and computation. In this work, we present a method for optimal 2D image tile sizing using constraint programming. Unlike previous methods, ours accurately models DMA data transfer times and parallel scheduling overheads with non-linear constraints. Our experiments with a binomial filter demonstrate that we can compute the optimal tiling dimensions that minimize the execution time for different image sizes and internal memory constraints. This technique provides invaluable information for both application developers and system architects that can quickly explore design trade-offs.
Keywords
"Kernel","Computational modeling","Data models","Analytical models","Linear regression","Data transfer","Optimization"
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2015 Conference on
Type
conf
DOI
10.1109/DASIP.2015.7367256
Filename
7367256
Link To Document