Towards optimal FPGA implementation of lattice-ladder neuron and its training circuit

The FPGA implementation of lattice-ladder multilayer perceptron with its training algorithm seems attractive, however there is a lack of experimental results on its efficiency. The main aim of this investigation was to optimize the latency and DSP block usage for the normalized lattice-ladder neuron (LLN) and its simple gradient training algorithm implementation on FPGA. Four alternative regressor lattices to be used in LLN training were considered and experimentally evaluated. The optimal resource sharing was approached by the LLN data flow graph partitioning into DSP block subgraphs. The experiments were performed by varying the number of synapses and the order of lattice-ladder filters. Recommendations for particular LLN implementation cases were given.