Fault-tolerant architecture and CAD algorithm for field-programmable pin-constrained digital microfluidic biochips

Advent of digital microfluidic embedded biochips has revolutionized accomplishment of laboratory procedures. Digital microfluidic biochips provide general-purpose assay execution along with several advantages compared with traditional benchtop chemistry procedures; advantages of these modern devices encompass automation, miniaturization and lower costs. However these embedded systems are vulnerable to various types of faults which can adversely affect the integrity of assay execution outcome. This paper addresses fault tolerance of field-programmable pin-constrained digital microfluidic biochips from various aspects; evaluating effects of faulty mix modules, faulty Storage / Split / Detection (SSD) modules and faulty regions within routing paths. The simulation results show that in case of faulty mixing modules the operation times were retained however the 5 % advantage in routing times contributes to 1 % improvement of total bioassay execution time; considering overheads incurred by faulty mixing modules, the results show no overhead in operation times and 20 % overhead in routing times which in turn incur 2 % overhead on total bioassay execution time. In case of faulty SSD modules the operation time remains the same however as a result of 19 % advantage in routing times the total bioassay execution time shows 2 % improvement; regarding the overheads incurred by faulty SSD modules it is observed that despite the 4 % overhead in routing times there is no overhead with the total bioassay execution time.