Live demostration: ‘Ripple sort’ algorithm, circuit implementation and verification using VHDL synthesisable testbench verification technique

Summary form only given. This demonstration centered around the, design, simulation and verification of the `Ripple Sort Algorithm and circuit implementation´ using VHDL synthesizable testbench verification techniques. The purpose of this demonstration is to show; the advantages and benefits for using synthesizable testbench verification techniques by means of inexpensive off-the-shelf tools. How an ASIC/FPGA design can be automated, checked for bugs and rapidly verified.