Off-Chip/On-chip Gateway Architecture for Mixed-Criticality Systems Based on Networked Multi-core Chips

Multi-core processors promise improved performance and a higher physical integration by combining functions of different criticality levels in one platform. Networked multi-core chips are required to achieve a system reliability beyond the reliability of a single chip and to satisfy resource requirements exceeding the capacity of a single chip. As a consequence, hierarchical platforms emerge in which cores inside a multi-core chip interact by on-chip networks whereas multi-core chips are interconnected by off-chip networks. This paper presents gateways for establishing such a hierarchical platform. We support message-based NoCs and off-chip networks with different timing models, while also supporting real-time guarantees, fault isolation and protocol transformations. The gateways are implemented in a simulation environment based on GEM5/GARNET and experimentally evaluated.