LATED: Lifetime-Aware Tag for Enduring Design

Nowadays, leakage energy constitutes up to80% of total cache energy consumption and tag array isresponsible for a considerable fraction of static energyconsumption. An approach to reduce static energyconsumption is to replace SRAMs by STT-RAMs with nearzero leakage power. However, a problem of an STT-RAMcell is its limited write endurance. In spite of previousstudies which have targeted the data array, in this studySTT-RAMs are used in the L1 tag array. To solve the writeendurance problem, this paper proposes an STTRAM/SRAM tag architecture. Considering the spatiallocality of memory references, the lower significant bitlinesof the tag update more. The SRAM part handles theupdates in the bit-lines which their lifetime is less than thedesired lifetime. The proposed architecture is evaluated bythe gem5 simulator running Mibench benchmark suits. The evaluation results recommend implementing less than30% of bit-lines of the STT-RAM-based tag array bySRAMs for a 5-year lifetime. Moreover, the static energyconsumption is reduced up to 82 % in comparison withSRAM tag array.